Freescale Semiconductor /MKL46Z4 /DMA /DCR2

Link Channel 2

0 (00): DMA Channel 0

1 (01): DMA Channel 1

2 (10): DMA Channel 2

3 (11): DMA Channel 3

Link Channel 1

0 (00): DMA Channel 0

1 (01): DMA Channel 1

2 (10): DMA Channel 2

3 (11): DMA Channel 3

Link Channel Control

0 (00): No channel-to-channel linking

1 (01): Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.

2 (10): Perform a link to channel LCH1 after each cycle-steal transfer

3 (11): Perform a link to channel LCH1 after the BCR decrements to 0.

Disable Request

0 (0): ERQ bit is not affected.

1 (1): ERQ bit is cleared when the BCR is exhausted.

Destination Address Modulo

0 (0000): Buffer disabled

1 (0001): Circular buffer size is 16 bytes

2 (0010): Circular buffer size is 32 bytes

3 (0011): Circular buffer size is 64 bytes

4 (0100): Circular buffer size is 128 bytes

5 (0101): Circular buffer size is 256 bytes

6 (0110): Circular buffer size is 512 bytes

7 (0111): Circular buffer size is 1 KB

8 (1000): Circular buffer size is 2 KB

9 (1001): Circular buffer size is 4 KB

10 (1010): Circular buffer size is 8 KB

11 (1011): Circular buffer size is 16 KB

12 (1100): Circular buffer size is 32 KB

13 (1101): Circular buffer size is 64 KB

14 (1110): Circular buffer size is 128 KB

15 (1111): Circular buffer size is 256 KB

Source Address Modulo

0 (0000): Buffer disabled

1 (0001): Circular buffer size is 16 bytes.

2 (0010): Circular buffer size is 32 bytes.

3 (0011): Circular buffer size is 64 bytes.

4 (0100): Circular buffer size is 128 bytes.

5 (0101): Circular buffer size is 256 bytes.

6 (0110): Circular buffer size is 512 bytes.

7 (0111): Circular buffer size is 1 KB.

8 (1000): Circular buffer size is 2 KB.

9 (1001): Circular buffer size is 4 KB.

10 (1010): Circular buffer size is 8 KB.

11 (1011): Circular buffer size is 16 KB.

12 (1100): Circular buffer size is 32 KB.

13 (1101): Circular buffer size is 64 KB.

14 (1110): Circular buffer size is 128 KB.

15 (1111): Circular buffer size is 256 KB.

Start Transfer

0 (0): DMA inactive

1 (1): The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.

Destination Size

0 (00): 32-bit

1 (01): 8-bit

2 (10): 16-bit

3 (11): Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)

Destination Increment

0 (0): No change to the DAR after a successful transfer.

1 (1): The DAR increments by 1, 2, 4 depending upon the size of the transfer.

Source Size

0 (00): 32-bit

1 (01): 8-bit

2 (10): 16-bit

3 (11): Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)

Source Increment

0 (0): No change to SAR after a successful transfer.

1 (1): The SAR increments by 1, 2, 4 as determined by the transfer size.

Enable asynchronous DMA requests

0 (0): Disabled

1 (1): Enabled

Auto-align

0 (0): Auto-align disabled

1 (1): If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.

Cycle Steal

0 (0): DMA continuously makes read/write transfers until the BCR decrements to 0.

1 (1): Forces a single read/write transfer per request.

Enable Peripheral Request

0 (0): Peripheral request is ignored.

1 (1): Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.

Enable Interrupt on Completion of Transfer

0 (0): No interrupt is generated.

1 (1): Interrupt signal is enabled.